H838532H datasheet(176/508 Pages) RENESAS

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Section 6 ROM

Rev. 1.00 May 30, 2008 Page 156 of 484

REJ09B0436-0100

6.8

Power-Down States for Flash Memory

In user mode, the flash memory will operate in either of the following states:

• Normal operating mode

The flash memory can be read and written to at high speed.

• Power-down operating mode

The power supply circuit of the flash memory is partly halted and can be read under low power

consumption.

• Standby mode

All flash memory circuits are halted.

Table 6.19 shows the correspondence between the operating modes of this LSI and the flash

memory. In subactive mode, the flash memory can be set to operate in power-down mode with the

PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from

power-down mode or standby mode, a period to stabilize the power supply circuits that were

stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to

STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the external

clock is being used.

Table 6.19

Flash Memory Operating States

Flash Memory Operating State

LSI Operating State

PDWND = 0 (Initial value)

PDWND = 1

Active mode

Normal operating mode

Subactive mode

Power-down mode

Normal operating mode

Sleep mode

Normal operating mode

Subsleep mode

Standby mode

Watch mode

Standby mode

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