H838532H datasheet(315/508 Pages) RENESAS

315 / 508 page

Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 295 of 484

REJ09B0436-0100

Bit 7: Transmit interrupt enable (TIE)

Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when

transmit data is transferred from the transmit data register (TDR) to the transmit shift register

(TSR), and bit TDRE in the serial status register (SSR) is set to 1.

TXI can be released by clearing bit TDRE or bit TIE to 0.

Bit 7

TIE

Description

Transmit data empty interrupt request (TXI) disabled

(initial value)

Transmit data empty interrupt request (TXI) enabled

Bit 6: Receive interrupt enable (RIE)

Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive

error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)

to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.

There are three kinds of receive error: overrun, framing, and parity.

RXI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing

bit RIE to 0.

Bit 6

RIE

Description

Receive data full interrupt request (RXI) and receive error interrupt

request (ERI) disabled

(initial value)

Receive data full interrupt request (RXI) and receive error interrupt

request (ERI) enabled

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