H8SX1663 datasheet(180/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 128 of 1102

REJ09B0294-0100

5.8

Usage Notes

5.8.1

Conflict between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective

after execution of the instruction.

When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an

interrupt is generated during execution of the instruction, the interrupt concerned will still be

enabled on completion of the instruction, and so interrupt exception handling for that interrupt will

be executed on completion of the instruction. However, if there is an interrupt request with priority

over that interrupt, interrupt exception handling will be executed for the interrupt with priority,

and another interrupt will be ignored. The same also applies when an interrupt source flag is

cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared

to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while

the interrupt is masked.

Internal

address bus

Internal

write signal

TCIEV

TCFV

TCIV

interrupt signal

TIER_0 write cycle by CPU

TCIV exception handling

TIER_0 address

Figure 5.7 Conflict between Interrupt Generation and Disabling

Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to

activate the DTC, DTC activation and the interrupt exception handling by the CPU are both

executed. When changing the DTC enable bit, make sure that an interrupt is not requested.

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