H8SX1663 datasheet(176/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 124 of 1102

REJ09B0294-0100

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Priority Determination

The DTC activation source is selected according to the default priority, and the selection is not

affected by its mask level or priority level. For respective priority levels, see table 8.1, Interrupt

Sources, DTC Vector Addresses, and Corresponding DTCEs.

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Operation Order

If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the

CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is

selected as the DTC or DMAC activation source or CPU interrupt source, respective operations

are performed independently.

Table 5.6 lists the selection of interrupt sources and interrupt source clear control by setting the

DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the

DISEL bit in MRB of the DTC.

Table 5.6

Interrupt Source Selection and Clear Control

DMAC Setting

DTC Setting

Interrupt Source Selection/Clear Control

DTA

DTCE

DISEL

DMAC

DTC

CPU

√

[Legend]

√: The corresponding interrupt is used. The interrupt source is cleared.

(The interrupt source flag must be cleared in the CPU interrupt handling routine.)

O: The corresponding interrupt is used. The interrupt source is not cleared.

X: The corresponding interrupt is not available.

*: Don't care.

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Usage Note

The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in

table 5.6, when the DTC or DMAC reads/writes the prescribed register.

To initiate multiple channels for the DTC with the same interrupt, the same priority (DTCP =

DMAP) should be assigned.

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