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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7052 데이터시트(PDF) 242 Page - Renesas Technology Corp |
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SH7052 데이터시트(HTML) 242 Page - Renesas Technology Corp |
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242 / 919 page  216 Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C) TCR9A Bit: 7 6 5 43210 — TRG3BEN EGSELB1 EGSELB0 — TRG3AEN EGSELA1 EGSELA0 Initial value: 0 0 0 00000 R/W: R R/W R/W R/W R R/W R/W R/W TCR9B Bit: 7 6 5 43210 — TRG3DEN EGSELD1 EGSELD0 — TRG3CEN EGSELC1 EGSELC0 Initial value: 0 0 0 00000 R/W: R R/W R/W R/W R R/W R/W R/W TCR9C Bit: 7 6 5 43210 —— EGSELF1 EGSELF0 —— EGSELE1 EGSELE0 Initial value: 0 0 0 00000 R/W: R R R/W R/W R R R/W R/W • Bit 7—Reserved: This bit always reads 0. The write value should always be 0. • Bit 6—Trigger Channel 3BEN, 3DEN (TRG3BEN, TRG3DEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 6: TRG3xEN Description 0 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) 1 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled x = B or D |
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