SH7708 datasheet(131/633 Pages) RENESAS

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113

When the priorities for multiple interrupt sources are set to the same level and such interrupts are

generated at the same time, they are handled according to the default order listed in table 6.4.

Updating of interrupt priority level setting registers A and B should only be performed when the

BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acknowledgment, first

read one or other of the interrupt priority level setting registers, then clear the BL bit to 0. This

will secure the necessary timing internally.

Table 6.4

Interrupt Exception Vectors and Rankings

Interrupt Source

INTEVT

Code

Interrupt Priority

(Initial Value)

IPR (Bit

Numbers)

Priority within

IPR Setting Unit

Default

Priority

NMI

H'1C0

—

High

IRL

IRL3–IRL0 = 0000 H'200

—

IRL3–IRL0 = 0001 H'220

—

IRL3–IRL0 = 0010 H'240

—

IRL3–IRL0 = 0011 H'260

—

IRL3–IRL0 = 0100 H'280

—

IRL3–IRL0 = 0101 H'2A0

—

IRL3–IRL0 = 0110 H'2C0

—

IRL3–IRL0 = 0111 H'2E0

—

IRL3–IRL0 = 1000 H'300

—

↓

IRL3–IRL0 = 1001 H'320

—

IRL3–IRL0 = 1010 H'340

—

IRL3–IRL0 = 1011 H'360

—

IRL3–IRL0 = 1100 H'380

—

IRL3–IRL0 = 1101 H'3A0

—

IRL3–IRL0 = 1110 H'3C0

—

TMU0

TUNI0*1

H'400

0–15 (0)

IPRA (15–12) —

TMU1

TUNI1*1

H'420

0–15 (0)

IPRA (11–8) —

TMU2

TUNI2*1

H'440

0–15 (0)

IPRA (7–4)

High

TMU2

TICPI2*2

H'460

0–15 (0)

IPRA (7–4)

Low

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