7220 datasheet(45/303 Pages) RENESAS

45 / 303 page

2-18

FUNCTIONAL DESCRIPTION

2.3 Memory assignment

7220 Group User’s Manual

(4)

Border selection register (address 00E516)

The border selection register is assigned to address 00E516. This register consists of 8 bits, and is

used to set the border for blocks 1 and 2 by using one bit each. Bits 1 and 3 to 7 are not used.

(5)

Color registers (addresses 00E616 to 00E916)

Color registers 0 to 3 are assigned to addresses 00E616 to 00E916. All color registers consist of 8 bits,

and are used to set character output, blank output and character background color by CRT output

(R, G, B, OUT1). Bit 0 is not used.

(6)

CRT control register (address 00EA16)

The CRT control register is assigned to address 00EA16. This register consists of 8 bits, and is used

to set display on/off for each block. Bits 3 to 6 are not used.

(7)

CRT port control register (address 00EC16)

The CRT port control register is assigned to address 00EC16. This register consists of 8 bits, and is

used to set the input polarity (HSYNC and VSYNC) and the output polarity (R, G, B, OUT1 and OUT2).

2.3.9 A-D control registers (addresses 00EE16 and 00EF16)

The A-D control register 1 is assigned to address 00EE16, the A-D control register 2 is assigned to address

00EF16. Both registers consist of 8 bits

The A-D control register 1 is used to select analog input pins and hold the results of comparator operation.

Bits 3 and 5 to 7 are not used.

The A-D control register 2 is used to set the internal analog voltage. Bits 6 and 7 are not used.

2.3.10 Timer registers (addresses 00F016 to 00F316)

The timer registers are assigned to addresses 00F016 to 00F316. Both the timer and timer latch are written

in this area when writing, but only the timer is read when reading.

To write data to address 00F116, for example, the data are stored to the timer 2 latch and timer 2. After

that, the timer 2 contents are decremented by synchronizing with the clock pulse but the timer 2 latch

contents are not changed. Accordingly, when reading data at address 00F116, the contents of timer 2 is

read out at the time.

Fig. 2.3.7 Access to timer registers

At read access

Data loading at timer 2

overflow

Timer 2 latch

Timer 2

Counting

(down count)

Reading the contents of timer 2

Data setting

Timer 2

Timer 1

Timer 3

Timer 4

Addresses

00F016

00F116

00F216

00F316

7220 데이터시트(PDF) 45 Page - Renesas Technology Corp

7220 데이터시트(HTML) 45 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL