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7220 Group User’s Manual

2.8 Multi-master I2C-BUS interface

2.8.2 Multi-master I2C-BUS interface-related registers

(1)

I2C data shift register (S0: address 00D716)

The I2C data shift register (S0 : address 00D716) is an 8-bit shift register to store receive data and

write transmit data.

When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization

with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit

to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL

clock, and each time one-bit data is input, the data of this register are shifted one bit to the left.

The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register

(address 00DA16) is “1.” The bit counter is reset by a write instruction to the I2C data shift register.

When both the ESO bit and the MST bit of the I2C status register (address 00F916) are “1,” the SCL

is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift

Figure 2.8.2 shows the I2C data shift register.

Fig. 2.8.2 I2C data shift register

b7 b6 b5 b4 b3 b2 b1 b0

I C data shift register (S0) [Address 00D716]

Functions

After reset

I C Data Shift Register

This is an 8-bit shift register to store

receive data and write transmit data.

Indeterminate

Note:

To write data into the I C data shift register after setting the MST bit to

“0” (slave mode), keep an interval of 8 machine cycles or more.

Name

D0 to D7

FUNCTIONAL DESCRIPTION

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