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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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7220 데이터시트(PDF) 86 Page - Renesas Technology Corp |
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7220 데이터시트(HTML) 86 Page - Renesas Technology Corp |
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86 / 303 page  2-59 7220 Group User’s Manual 2.8 Multi-master I2C-BUS interface (3) START/STOP condition detect conditions The START/STOP condition detect conditions are shown in Figure 2.8.11 and Table 2.8.3. Only when the 3 conditions of Table 10 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” is generated to the CPU. Hold time Setup time SCL SDA (START condition) SDA (STOP condition) SCL release time Hold time Setup time Fig. 2.8.11 START condition/STOP condition detect timing diagram Table 2.8.3 START condition/STOP condition detect conditions Standard clock mode 6.5 µ s (26 cycles) < SCL release time 3.25 µ s (13 cycles) < Setup time 3.25 µ s (13 cycles) < Hold time High-speed clock mode 1.0 µ s (4 cycles) < SCL release time 0.5 µ s (2 cycles) < Setup time 0.5 µ s (2 cycles) < Hold time Note: Absolute time at f = 4 MHz. The value in parentheses denotes the number of f cycles. FUNCTIONAL DESCRIPTION |
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