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7220 데이터시트(PDF) 75 Page - Renesas Technology Corp

부품명 7220
상세설명  8-BIT SINGLE-CHIP MICROCOMPUTER
PDF  303 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7220 데이터시트(HTML) 75 Page - Renesas Technology Corp

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7220 Group User’s Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
I C address register
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Noise
elimination
circuit
Serial
data
(SDA)
Address comparator
b7
I C data shift register
b0
Data
control
circuit
System clock
(
φ)
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
MST TRX BB
PIN
AL AAS AD0 LRB
b0
I C status
register
S1
b7
b0
BSEL1 BSEL0
10BIT
SAD
ALS
BC2 BC1 BC0
S1D
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
b7
b0
ACK
ACK
BIT
FAST
MODE
CCR4 CCR3 CCR2 CCR1 CCR0
Internal data bus
Clock division
S0
S2
S0D
AL
circuit
ESO
2
2
I C clock control register
2
2
I C control register
2
Fig. 2.8.1 Block diagram of multi-masteer I2C-BUS interface
2.8.1 Construction of multi-master I2C-BUS interface
The multi-master I2C-BUS interface consists of the following :
q I2C address register
q I2C data shift register
q I2C clock control register
q I2C control register
q I2C status register
q Other control circuits
The data transfer with the internal CPU is performed via data bus, the data transfer with an external device
is performed via ports P11–P14. When using multi-master I2C-BUS interface, these ports P11–P14 are
assigned to the following functions.
q P11: Multi-master I2C-BUS interface Synchronous clock input/output pin 1 (SCL1)
q P12: Multi-master I2C-BUS interface Synchronous clock input/output pin 2 (SCL2)
q P13: Multi-master I2C-BUS interface data input/output pin 1 (SDA1)
q P14: Multi-master I2C-BUS interface data input/output pin 2 (SDA2)
The shift clock to determine the transfer speed of serial data is selected by the I2C clock control register
(refer to “Figure 2.8.4”).
A serial data and a serial clock is referred as “SDA,” “SCL” respectively, hereafter.



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