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7220 Group User’s Manual

FUNCTIONAL DESCRIPTION

2.8 Multi-master I2C-BUS interface

(2)

I2C address register (S0D: address 00D816)

The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In

the addressing mode, the slave address written in this register is compared with the address data

to be received immediately after the START condition are detected.

s Bit 0: Read/write bit (RBW)

Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode,

the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the

I2C address register.

The RBW bit is cleared to “0” automatically when the stop condition is detected.

s Bits 1 to 7: Slave address (SAD0–SAD6)

These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing

mode, the address data transmitted from the master is compared with the contents of these bits.

Figure 2.8.3 shows the I2C address register.

Fig. 2.8.3 I2C address register

b7 b6 b5 b4 b3 b2 b1 b0

Read/write bit

(RBW)

Slave address

(SAD0 to SAD6)

0: Read

1: Write

The address data transmitted from

the master is compared with the

contents of these bits.

I2C Address Register

I2C address register (S0D) [Address 00D816]

Name

Functions

After reset RW

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