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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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7733 데이터시트(PDF) 346 Page - Renesas Technology Corp |
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7733 데이터시트(HTML) 346 Page - Renesas Technology Corp |
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346 / 940 page  CONNECTING EXTERNAL DEVICES 7733 Group User’s Manual 12–21 Fig. 12.4.2 Timing when hold state is accepted and terminated (1) External data bus Data length External data bus width Software wait 16 8, 16 No wait, Not in use q State when “L” level is input to pin HOLD Wait 1, Wait 0 8, 16 8 ALE E External address bus/ External data bus HLDA HOLD External address bus Address B 1 ! 1 1 ! 1 Sampling timing Bus is in use. Bus is not in use. Note: The same operation is performed independent of the software wait (no wait, wait 0, or wait 1). This diagram shows the operation when no wait is selected. Because the bus is not in use, the address which was output immediately before is output again, instead of a new address. R/W Clock 1 Address A Data <<When “L” level is input to pin HOLD while bus is not in use>> BHE Floating Address A Floating Floating Bus is in use. Hold state 12.4 Hold function |
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