7733 datasheet(411/940 Pages) RENESAS

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7733 Group User’s Manual

17–4

17.1.2 Calculation ways for timing

When expanding memory, use a memory of which specifications satisfy the following timing requirements:

address access time (ta(AD)) and data setup time for writing data (tsu(D)). Calculation ways for ta(AD) and

tsu(D) are described below.

Address access time of external memory [ta(AD)]

ta(AD) = td(An/A-E) + tw(EL) – tsu(D-E)

– (address decode timeV1 + address latch delay timeV2)

td(An/A-E) : td(An-E) or td(A-E)

address decode timeV1: time necessary for validating a chip select signal after an address is decoded

address latch delay timeV2: delay time necesarry for latching an address

(This is not necessary on the minimum model.)

Data setup time of external memory for writing data [tsu(D)]

tsu(D) = tw(EL) – td(E-D)

Table 17.1.2 lists the calculation formulas and constants for each parameter in the above formulas. Figure

17.1.1 shows bus timing diagrams. Figure 17.1.2 shows the relationship between ta(AD) and 2•f(f2). Figure

17.1.3 shows the relationship between tsu(D) and 2•f(f2).

Table 17.1.2 Calculation formulas and constants for each parameter (Unit: ns)

Software wait

Wait bit

Wait selection bit

td(A-E)

td(An-E)

tw(EL)

tsu(D-E)

td(E-DQ)

Wait 1

Wait 0

No wait

0 or 1

– 30

2 ! 109

2•f(f2)

1 ! 109

2•f(f2)

– 28

3 ! 109

2•f(f2)

– 45

4 ! 109

2•f(f2)

– 30

Wait bit: Bit 2 at address 5E16

Wait selection bit: Bit 0 at address 5F16

Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0.”

17.1 Memory expansion

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