7733 datasheet(412/940 Pages) RENESAS

412 / 940 page

APPLICATIONS

7733 Group User’s Manual

17–5

Fig. 17.1.1 Bus timing diagrams

tsu(D-E)

When BYTE = “L” (External data bus = 16 bits wide)

ALE

High-order

address

Low-order address

td(An-E)

td(A-E)

tsu(D-E)

tw(EL)

When data is written

High-order

address

Low-order data

td(E-DQ)

Low-order address

When data is read

Middle-order

address

td(A-E)

Middle-order

address

High-order data

td(E-DQ)

R/W

When BYTE = “H” (External data bus = 8 bits wide)

Middle-order address

ALE

High-order

address

Low-order address

td(An-E)

td(A-E)

tsu(D-E)

tw(EL)

A0 to A7

A8 to A15

A16/D0 to A23/D7

High-order

address

Data

td(E-DQ)

Middle-order address

Low-order address

When data is written

When data is read

R/W

Data

ta(AD)

tsu(D)

tw(EL)

ta(AD)

tsu(D)

tw(EL)

A0 to A7

A8/D8 to A15/D15

A16/D0 to A23/D7

: Specifications of the 7733 Group

(The others are specifications of external

memory.)

17.1 Memory expansion

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