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7733 데이터시트(PDF) 413 Page - Renesas Technology Corp |
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7733 데이터시트(HTML) 413 Page - Renesas Technology Corp |
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413 / 940 page ![]() APPLICATIONS 7733 Group User’s Manual 17–6 Fig. 17.1.3 Relationship between tsu(D) and 2•f(f2) Fig. 17.1.2 Relationship between ta(AD) and 2•f(f2) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 600 700 800 900 893 768 670 593 529 476 431 393 359 330 304 281 261 243 226 211 197 184 173 624 535 465 410 364 326 294 267 243 222 204 187 173 160 148 137 127 118 110 338 285 243 210 182 160 140 124 110 97 86 76 67 60 52 46 40 35 30 No wait Wait 1 is valid. Wait 0 is valid. [ns] External clock input frequency 2•f(f2) [MHz] g Address decode time and address latch delay time are not considered. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 100 200 300 400 500 496 425 369 325 288 258 232 210 191 175 160 147 135 125 115 106 98 91 85 175 147 125 106 91 78 67 58 50 42 36 30 25 20 15 11 8 5 No wait Wait 1 or Wait 0 is valid. External clock input frequency 2•f(f2) [MHz] [ns] 210 17.1 Memory expansion |
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