7733 datasheet(219/940 Pages) RENESAS

219 / 940 page

SERIAL I/O

7733 Group User’s Manual

8–16

000

Receive data (9 bits)

Receive data (8 bits)

Receive data (7 bits)

(Transfer data length : 9 bits)

During UART mode

(Transfer data length : 8 bits)

During UART mode

(Transfer data length : 7 bits)

Same value as bit

7 in low-order byte

Same value as bit

6 in low-order byte

High-order byte

(addresses 37 16, 3F16, 6B16)

Low-order byte

(addresses 36 16, 3E16, 6A16)

The UARTi receive register is used to convert serial data, which is input from the RxDi pin, into parallel

data. This register takes a signal which is input from the RxDi pin by the 1 bit synchronously with the

transfer clock.

The UARTi receive buffer register is used to read receive data. When reception is completed, the receive

data which is taken into the UARTi receive register is automatically transferred to the UARTi receive buffer

in the UARTi receive register before data which has been transferred to the UARTi receive buffer register

is read out (in other words, when an overrun error occurs).

When “MSB first” is selected in the clock synchronous serial I/O mode, bit position of data in the UARTi

receive buffer register is reversed, and then this data is read out as the receive data. (Refer to section

“8.3.2 Transfer data format.”) Receive operation itself is the same whichever format is selected, “LSB

first” or “MSB first.”

The UARTi receive buffer register is initialized when the receive enable bit (bit 2 at addresses 3516, 3D16

and 6916) is set to “1” after clearing it to “0.”

Figure 8.2.12 shows the contents of the UARTi receive buffer register when reception is completed.

Fig. 8.2.12 Contents of UARTi receive buffer register when reception is completed

8.2 Block description

7733 데이터시트(PDF) 219 Page - Renesas Technology Corp