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7733 데이터시트(PDF) 233 Page - Renesas Technology Corp |
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7733 데이터시트(HTML) 233 Page - Renesas Technology Corp |
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233 / 940 page ![]() SERIAL I/O 7733 Group User’s Manual 8–30 [When not using interrupts] [When using interrupts] A UARTi transmission interrupt request occurs when the UARTi transmission buffer register becomes empty. UARTi transmission interrupt g UART0 transmission buffer register (address 32 16) UART1 transmission buffer register (address 3A 16) UART2 transmission buffer register (address 66 16) b7 b0 Writing of next transmit data Transmit data is set here. UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) b7 Transmission buffer empty flag 0: Data is present in the transmission buffer register. 1: No data is present in the transmission buffer register. (Next transmit data can be written.) Checking status of the UARTi transmission buffer register 1 This diagram indicates bits and registers required for processing. Refer to Figure 8.3.8 for details about the change of flag status and the occurrence timing of an interrupt request. b0 Fig. 8.3.5 How to write data after transmission is started 8.3 Clock synchronous serial I/O mode |
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