7733 datasheet(234/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–31

[When not using interrupts]

[When using interrupts]

UARTi transmission interrupt

UART0 transmission interrupt control register (address 71 16)

UART1 transmission interrupt control register (address 73 16)

A-D/UART2 trans./rece. interrupt control register (address 70 16)

Interrupt request bit

Checking the start of transmission

UART0 transmit/receive control register 0 (address 34 16)

UART1 transmit/receive control register 0 (address 3C 16)

UART2 transmit/receive control register 0 (address 68 16)

Checking the completion of transmission

Transmission register empty flag

0: Transmission is in progress.

1: Transmission is completed.

Processing at completion of transmission

No interrupt request has occurred.

Interrupt request has occurred.

(Transmission has been started.)

A UARTi transmission interrupt request

occurs when the transmission is started.

This diagram indicates bits and registers required

for processing.

Refer to Figure 8.3.8 for details about the change

of flag status and the occurrence timing of an

interrupt request.

Note: Nothing is allocated to bits 7 to 4 of the UART2

transmit/receive control register 0.

Fig. 8.3.6 How to detect of transmit completion

8.3 Clock synchronous serial I/O mode

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