CS8422-DNZ datasheet(66/82 Pages) CIRRUS

66 / 82 page

DS692PP1

CS8422

12.3.2

Isolating Transformer Requirements

Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on

transformer selection

12.4

Channel Status Buffer Management

12.4.1

AES3 Channel Status (C) Bit Management

The CS8422 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels (5 x 2 x 8

= 80 bits). The user may read from this buffer’s RAM through the control port.

The buffering scheme involves two buffers, named D and E, as shown in Figure 33. The MSB of each byte

represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port

address 23h) is the consumer/professional bit for channel status block A.

The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocks

of data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the first

five bytes of C data.

The complete C data may be obtained through the C pin in Hardware Mode and through one of the GPO

pins in Software Mode. The C data is serially shifted out of the CS8422 clocked by the rising and falling

edges of OLRCK or VLRCK.

.01

µF

CS8422

AGND

Vin

R2 =

247.5

Vin

R1 = 75 – R2

Ω

Coax

(1)

(2)

Figure 31. Receiver Input Attenuation – Single-ended Input

110

Ω

Twisted

Pair

CS8422

RXP

RXN

Rin

AGND

Vin+

Vin-

(1) R =

726

Vin+ - Vin-

(2) Rin = 55 - R

Figure 32. Receiver Input Attenuation – Differential Input

CS8422-DNZ 데이터시트(PDF) 66 Page - Cirrus Logic

CS8422-DNZ 데이터시트(HTML) 66 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

데이터시트 다운로드

링크 URL