CS8422-DNZ datasheet(34/82 Pages) CIRRUS

34 / 82 page

DS692PP1

CS8422

6.7.1

Hardware Mode Control

In Hardware Mode, AUDIO is output on the V/AUDIO pin when a 20 k

Ω resistor is connected from the

V/AUDIO pin to VL.

6.7.2

Software Mode Control

In Software Mode, the AUDIO signal is available through the GPO pins. See “GPO Control 1 (05h)” on

page 50 for more details.

6.8

Format Detection (Software Mode Only)

In Software Mode, the CS8422 can automatically detect various serial audio input formats. The Format De-

tect Status register (12h) is used to indicate a detected format. The register will indicate if uncompressed

PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Additionally, the

IEC61937 Pc/Pd burst preambles are available in registers 2Dh-30h. See the register descriptions for more

information.

6.9

Interrupts (Software Mode Only)

The INT signal, available in Software Mode, indicates when an interrupt condition has occurred and may be

output on one of the GPOs. It can be set through bits INT[1:0] in the Control1 register (02h) to be active low,

active high, or open-drain active low. This last mode is used for active low, wired-OR hook-ups, with multiple

peripherals connected to the microcontroller interrupt input pin.

Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source

may be masked off through mask register bits. In addition, some sources may be set to rising edge, falling

edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the mi-

crocontroller, many different configurations are possible, depending on the needs of the equipment design-

er. Refer to the register descriptions for the Interrupt Unmasking (0Fh), Interrupt Mode (10h), and Interrupt

Status (14h) registers

6.10

Channel Status and User Data Handling

“Channel Status Buffer Management” on page 66 describes the overall handling of Channel Status and

User data.

6.10.1

Hardware Mode Control

In Hardware Mode, Received Channel Status (C), and User (U) bits are output on the C and TX/U pins

(U data output must be selected on the TX/U pin, see “Hardware Mode Control” on page 39 for details).

OLRCK2 and RCBL are made available to qualify the C and U data output. Figure 19 illustrates timing of

the C and U data and their related signals.

6.10.2

Software Mode Control

In Software Mode, several options are available for accessing the Channel Status and User data that is

encoded in the received AES3 or SPDIF data.

The first option allows access directly through registers. The first 5 bytes of the Channel Status block are

decoded into the “Channel Status Registers (23h - 2Ch)”. Registers 23h-27h contain the A channel status

data. Registers 28h-2Ch contain the B channel status data.

Received Channel Status (C), User (U), and EMPH bits may also be serial outputs to the GPO pins by

appropriately setting the GPOxSEL bits in the “GPO Control 1 (05h)” registers. OLRCK and RCBL can be

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