CS8422-DNZ datasheet(30/82 Pages) CIRRUS

30 / 82 page

DS692PP1

CS8422

6.2.2.1

Single-Ended Input Mode

When the receiver input multiplexer is set to Single-Ended Mode, the receiver inputs can be switched be-

tween operation as comparator inputs or digital inputs.

Receiver Input Mode 1 (Analog Sensitivity Mode)

If Mode 1 is selected, the inputs are biased at VA/2 and should be coupled through a capacitor. The rec-

ommended value for the AC coupling capacitors is 0.01 µF to 0.1 µF. The recommended dielectrics for

the AC coupling capacitors are C0G or X7R.

When the receiver input multiplexer is in Mode 1, the receiver input pins allow very low amplitude signals

to be decoded reliably. In this mode, the maximum allowable input amplitude is determined by VA, which

is nominally 3.3 volts. If input amplitudes greater than 3.3 Volts to a single pin of the receiver input multi-

plexer are required, then attenuation is necessary prior to the receiver input to avoid damage to the part

(See “Attenuating Input signals” on page 65 for more details). Figure 17 shows the input structure of the

receiver in Single-Ended Mode.

Figure 17. Single-Ended Receiver Input Structure, Receiver Mode 1

Receiver Input Mode 2 (Digital Sensitivity Mode)

If Mode 2 is selected, the receiver inputs should be driven by a digital signal referenced to VA. In this

mode, the selected receiver input is not biased, and does not require the use of an AC coupling capacitor

(as with the use of a typical optical receiver output).

When the receiver input multiplexer is in Mode 2 the specifications for VIH/VIL apply (see “Switching Spec-

ifications” on page 17 for more details).

6.2.2.2

Differential Input Mode

When the receiver input multiplexer is set to differential input mode, the inputs are biased at VA/2, and

require the use of AC coupling capacitors, as mentioned in Section 6.2.2.1. Figure 18 shows the structure

of the receiver in differential mode.

22 k

Ω

(22000/N)

Ω

22 k

Ω

AGND

RX[3:0]

(1500 + 1500/N)

Ω

(22000/N)

Ω

Note:

If RX[3:0] is selected by either the receiver MUX or the TX pass-through MUX, N=1.

If RX[3:0] is selected by both the receiver MUX and the TX pass-through MUX, N=2.

If RX[3:0] is not selected at all, N=0 (i.e. high impedance).

CS8422-DNZ 데이터시트(PDF) 30 Page - Cirrus Logic

CS8422-DNZ 데이터시트(HTML) 30 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

데이터시트 다운로드

링크 URL