 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
CS8422-DNZ 데이터시트(PDF) 21 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS8422-DNZ 데이터시트(HTML) 21 Page - Cirrus Logic |
|
|
21 / 82 page  DS692PP1 21 CS8422 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF. Notes: 16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RST Rising Edge to Start tirs 500 - µs Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs SDA Hold Time from SCL Falling (Note 16) thdd 10 - ns SDA Setup time to SCL Rising tsud 250 - ns Rise Time of SCL and SDA trc, trd - 1000 ns Fall Time SCL and SDA tfc, tfd -300 ns Setup Time for Stop Condition tsusp 4.7 - µs Acknowledge Delay from SCL Falling tack 300 1000 ns t buf t hdst t lo w t hd d t high t su d Sto p S t a r t SDA SC L t irs RS T t hdst t rc t fc t sust t susp St a r t Sto p Re p e a t e d t rd t fd t ack Figure 6. I²C Mode Timing |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
