 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
CS8422-DNZ 데이터시트(PDF) 69 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS8422-DNZ 데이터시트(HTML) 69 Page - Cirrus Logic |
|
|
69 / 82 page  DS692PP1 69 CS8422 12.6 Jitter Tolerance Figure 36 shows the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4 specifi- cation. CS8422 devices have been tested to pass this template. 12.7 Group Delay The group delay introduced by the CS8422 depends on the type of interface selected, and input and output sample rates of the sample rate converter. The expression for the group delay through the CS8422 with the use of the sam- ple rate converter is shown below, where the interface delay is 3 OLRCK periods in all modes except AES3 direct mode, in which it is 2 OLRCK periods. If the sample rate converter is not being used, then the approximate group delay will be equal to the interface delay. Figure 36. Jitter Tolerance Template TotalGroupDelay 8.7 Fsi -------- 5 Fso --------- InterfaceDelay ++ ⎝⎠ ⎛⎞ = |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
