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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATmega162 데이터시트(PDF) 135 Page - ATMEL Corporation |
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ATmega162 데이터시트(HTML) 135 Page - ATMEL Corporation |
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135 / 324 page  135 2513K–AVR–07/09 ATmega162/V Interrupt Vector (See “Interrupts” on page 57.) is executed when the OCF1B Flag, located in TIFR, is set. • Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 57.) is executed when the ICF1 Flag, located in TIFR, is set. Extended Timer/Counter Interrupt Mask Register – ETIMSK (1) Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer3 bits are described in this section. The remaining bits are described in their respective Timer sections. • Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 57.) is executed when the ICF3 Flag, located in TIFR, is set. • Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 57.) is executed when the OCF3A Flag, located in TIFR, is set. • Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 57.) is executed when the OCF3B Flag, located in TIFR, is set. • Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 57.) is executed when the TOV3 Flag, located in TIFR, is set. Timer/Counter Interrupt Flag Register – TIFR(1) Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective Timer sections. • Bit 7 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Table 56 on page 130 for the TOV1 Flag behavior when using another WGMn3:0 bit setting. Bit 7 6 5 4 3 2 1 0 TICIE3 OCIE3A OCIE3B TOIE3 – –ETIMSK Read/Write R R R/W R/W R/W R/W R R Initial Value 0 0 0 0 0 0 0 0 Bit 765 4321 0 TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 |
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