PCIMX258CJM4A datasheet(111/144 Pages) FREESCALE

111 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

111

3.7.18.2

ADC Timing Diagrams

Figure 82 represents the synchronization between the signals clk, soc, eoc, and the output bits in the usage

of the internal ADC. After a conversion cycle eoc is asserted, a new conversion begins only when the

assertion of soc is detected. Thus, if the soc signal is continuously asserted, the ADC undergoes successive

conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated.

Power Supply Requirements

Current consumption2

NVCC_ADC

QVDD

——

—

2.1

0.5

Power-down current

NVCC_ADC

QVDD

——

—

Touchscreen Interface

Expected plate resistance

—

100

—

1500

Switch drivers on

resistance

GND and VDD switches

—

Conversion Characteristics3

DNL4

fin = 1 kHz

—

+/–0.75

—

LSB

INL4

fin = 1 kHz

—

+/–2.0

—

LSB

Gain + Offset Error

—

+/–2

%FS

1 This comprises only the required initial dummy conversion cycle. Additional power-up time depends on the enadc, reset and

soc signals applied to the touchscreen controller.

2 This value only includes the ADC and the driver switches, but it does not take into account the current consumption in the

touchscreen plate. For example, if the plate resistance is 100 W, the total current consumption is about 33 mA.

3 At avdd = 3.3 V, dvdd = 1.2 V, Tjunction = 50 °C, fclk = 1.75 MHz, any process corner, unless otherwise noted.

4 Value measured with a –0.5 dBFS sinusoidal input signal and computed with the code density test.

Table 83. Touchscreen ADC Electrical Specifications (continued)

Parameter

Conditions

Min.

Typ.

Max.

Unit

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