MPC8308VMAGDA datasheet(39/88 Pages) FREESCALE

39 / 88 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0

Freescale Semiconductor

PCI Express

Figure 27. Minimum Transmitter Timing and Voltage Output Compliance Specifications

11.4.3

Differential Receiver (RX) Input Specifications

Table 35 defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins.

Table 35. Differential Receiver (RX) Input Specifications

Parameter

Symbol

Comments

Min

Typical

Max

Units

Notes

Unit interval

Each UPERX is 400 ps ±

300 ppm. UPERX does not

account for Spread

Spectrum Clock dictated

variations.

399.88

400

400.12

Differential peak-to-peak

output voltage

VRX-DIFFp-p

VPEDPPRX = 2*|VRX-D+ -

VRX-D-|

0.175

—

1.200

Minimum receiver eye

width

TRX-EYE

The maximum

interconnect media and

Transmitter jitter that can

be tolerated by the

Receiver can be derived

as TRX-MAX-JITTER = 1 -

UPEEWRX= 0.6 UI.

0.4

——UI

2, 3

[De-emphasized Bit]

566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX)

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

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