MPC8308VMAGDA datasheet(78/88 Pages) FREESCALE

78 / 88 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0

Freescale Semiconductor

Clocking

coherent system bus clock (csb_clk). Table 57 shows the expected frequency values for the CSB frequency

for select csb_clk to SYS_CLK_IN ratios.

21.3

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 58 shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in Table 58 should be considered as reserved.

NOTE

Core VCO frequency = core frequency

× VCO divider. The VCO divider,

which is determined by RCWLR[COREPLL], must be set properly so that

the core VCO frequency is in the range of 400–800 MHz.

Table 57. CSB Frequency Options

SPMF

csb_clk :Input Clock Ratio

Input Clock Frequency (MHz)

33.33

66.67

0010

2:1

133

0100

4:1

133

0101

5:1

125

Table 58. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk: csb_clk Ratio1

VCO Divider (VCOD)2

0–1

2–5

0000

PLL bypassed

(PLL off, csb_clk clocks core directly)

PLL bypassed

(PLL off, csb_clk clocks core directly)

nnnn

nn/a

n/a

0001

01:1

0001

01:1

0001

01:1

0001

1.5:1

0001

1.5:1

0001

1.5:1

0010

02:1

0010

02:1

0010

02:1

0010

2.5:1

0010

2.5:1

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