MPC8308VMAGDA datasheet(44/88 Pages) FREESCALE

44 / 88 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0

Freescale Semiconductor

Enhanced Local Bus

Figure 30 provides the AC test load for the local bus.

Figure 30. Local Bus AC Test Load

Local bus clock to output valid (Note: to be revisited)

tLBKHOV

—3

Local bus clock to output high impedance for LD (Note: to be

revisited)

tLBKHOZ

—4

Notes:

1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case

for clock one(1).

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from NVDD/2 of the rising/falling edge of LCLK0 to 0.4 × NVDD of the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

Table 37. Local Bus General Timing Parameters (continued)

Parameter

Symbol 1

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

NVDD/2

RL = 50 Ω

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