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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HCS12 데이터시트(PDF) 211 Page - Freescale Semiconductor, Inc |
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HCS12 데이터시트(HTML) 211 Page - Freescale Semiconductor, Inc |
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211 / 452 page  Glossary S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 211 Operation: (PC) + $0004 ⇒ PC Description: Never branches. LBRN is effectively a 4-byte NOP that requires three cycles to execute. LBRN is included in the instruction set to provide a complement to the LBRA instruction. The instruction is useful during program debug, to negate the effect of another branch instruction without disturbing the offset byte. A complement for LBRA is also useful in compiler implementations. Execution time is longer when a conditional branch is taken than when it is not, because the instruction queue must be refilled before execution resumes at the new address. Since the LBRN branch condition is never satisfied, the branch is never taken, and the queue does not need to be refilled, so execution time is always the smaller value. LBRN Long Branch Never LBRN CCR Details: S X HIN Z V C –––––––– Source Form Address Mode Object Code Access Detail HCS12 M68HC12 LBRN rel16 REL 18 21 qq rr OPO OPO |
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