HCS12 datasheet(49/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

4.3.1 No Movement

There is no data movement in the instruction queue during the cycle. This

occurs during execution of instructions that must perform a number of

internal operations, such as division instructions.

4.3.2 Latch Data from Bus (Applies Only to the M68HC12 Queue Implementation)

All instructions initiate fetches to refill the queue as execution proceeds.

However, a number of conditions, including instruction alignment and the

length of previous instructions, affect when the queue advances. If the

queue is not ready to advance when fetched information arrives, the

information is latched into the buffer. Later, when the queue does advance,

stage 1 is refilled from the buffer. If more than one latch cycle occurs before

the queue advances, the buffer is filled on the first latch event and

subsequent latch events are ignored until the queue advances.

4.3.3 Advance and Load from Data Bus

The content of queue is advanced by one stage, and stage 1 is loaded with

a word of program information from the data bus. The information was

requested two bus cycles earlier but has only become available this cycle,

due to access delay.

4.3.4 Advance and Load from Buffer (Applies Only to M68HC12 Queue Implementation)

The content of queue stage 1 advances to stage 2, and stage 1 is loaded

with a word of program information from the buffer. The information in the

buffer was latched from the data bus during a previous cycle because the

queue was not ready to advance when it arrived.

4.4 Changes in Execution Flow

During normal instruction execution, queue operations proceed as a

continuous sequence of queue movement cycles. However, situations arise

which call for changes in flow. These changes are categorized as resets,

interrupts, subroutine calls, conditional branches, and jumps. Generally

speaking, resets and interrupts are considered to be related to events

outside the current program context that require special processing, while

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