HCS12 datasheet(95/452 Pages) FREESCALE

95 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

example of a best-case system is a single-chip 16-bit system with no 16-bit

off-boundary data accesses to any locations other than on-chip RAM.

Many conditions can cause one or more instruction cycles to be stretched,

but the CPU is not aware of the stretch delays because the clock to the CPU

is temporarily stopped during these delays.

The following paragraphs explain the cycle code letters used and note

conditions that can cause each type of cycle to be stretched.

f — Free cycle. This indicates a cycle where the CPU

does not require use of the system buses. An f cycle

is always one cycle of the system bus clock. These

cycles can be used by a queue controller or the

background debug system to perform single cycle

accesses without disturbing the CPU.

g — Read 8-bit PPAGE register. These cycles are used

only with the CALL instruction to read the current

value of the PPAGE register and are not visible on the

external bus. Since the PPAGE register is an internal

8-bit register, these cycles are never stretched.

I — Read indirect pointer. Indexed indirect instructions

use this 16-bit pointer from memory to address the

operand for the instruction. These are always 16-bit

reads but they can be either aligned or misaligned.

These cycles are extended to two bus cycles if the

MCU is operating with an 8-bit external data bus and

the corresponding data is stored in external memory.

There can be additional stretching when the address

space is assigned to a chip-select circuit programmed

for slow memory. These cycles are also stretched if

they correspond to misaligned access to a memory

that is not designed for single-cycle misaligned

access.

i — Read indirect PPAGE value. These cycles are only

used with indexed indirect versions of the CALL

instruction, where the 8-bit value for the memory

expansion page register of the CALL destination is

fetched from an indirect memory location. These

cycles are stretched only when controlled by a

chip-select circuit that is programmed for slow

memory.

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