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HCS12 데이터시트(PDF) 26 Page - Freescale Semiconductor, Inc

부품명 HCS12
상세설명  HCS12 Microcontrollers
PDF  452 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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HCS12 데이터시트(HTML) 26 Page - Freescale Semiconductor, Inc

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S12CPUV2 Reference Manual, Rev. 4.0
26
Freescale Semiconductor
pending and are remembered, but operation continues uninterrupted until
the I bit is cleared.
When an interrupt occurs after interrupts are enabled, the I bit is
automatically set to prevent other maskable interrupts during the interrupt
service routine. The I bit is set after the registers are stacked, but before the
first instruction in the interrupt service routine is executed.
Normally, an RTI instruction at the end of the interrupt service routine
restores register values that were present before the interrupt occurred.
Since the CCR is stacked before the I bit is set, the RTI normally clears the
I bit, and thus re-enables interrupts. Interrupts can be re-enabled by clearing
the I bit within the service routine.
2.2.5.5 N Status Bit
The N bit shows the state of the MSB of the result. N is most commonly used
in two’s complement arithmetic, where the MSB of a negative number is 1
and the MSB of a positive number is 0, but it has other uses. For instance,
if the MSB of a register or memory location is used as a status flag, the user
can test status by loading an accumulator.
2.2.5.6 Z Status Bit
The Z bit is set when all the bits of the result are 0s. Compare instructions
perform an internal implied subtraction, and the condition codes, including
Z, reflect the results of that subtraction. The increment index register X
(INX), decrement index register X (DEX), increment index register Y (INY),
and decrement index register Y (DEY) instructions affect the Z bit and no
other condition flags. These operations can only determine = (equal) and
(not equal).
2.2.5.7 V Status Bit
The V bit is set when two’s complement overflow occurs as a result of an
operation.
2.2.5.8 C Status Bit
The C bit is set when a carry occurs during addition or a borrow occurs
during subtraction. The C bit also acts as an error flag for multiply and divide



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