HCS12 datasheet(44/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

3.11 Addressing More than 64 Kbytes

Some M68HC12 devices incorporate hardware that supports addressing a

larger memory space than the standard 64 Kbytes. The expanded memory

system uses fast on-chip logic to implement a transparent bank-switching

scheme.

Increased code efficiency is the greatest advantage of using a switching

scheme instead of a large linear address space. In systems with large linear

address spaces, instructions require more bits of information to address a

memory location, and CPU overhead is greater. Other advantages include

the ability to change the size of system memory and the ability to use

various types of external memory.

However, the add-on bank switching schemes used in other

microcontrollers have known weaknesses. These include the cost of

external glue logic, increased programming overhead to change banks, and

the need to disable interrupts while banks are switched.

The M68HC12 system requires no external glue logic. Bank switching

overhead is reduced by implementing control logic in the MCU. Interrupts do

not need to be disabled during switching because switching tasks are

incorporated in special instructions that greatly simplify program access to

extended memory.

MCUs with expanded memory treat the 16 Kbytes of memory space from

$8000 to $BFFF as a program memory window. Expanded-memory

architecture includes an 8-bit program page register (PPAGE), which allows

up to 256 16-Kbyte program memory pages to be switched into and out of

the program memory window. This provides for up to 4 Megabytes of paged

program memory.

The CPU12 instruction set includes call subroutine in expanded memory

(CALL) and return from call (RTC) instructions, which greatly simplify the

use of expanded memory space. These instructions also execute correctly

on devices that do not have expanded-memory addressing capability, thus

providing for portable code.

The CALL instruction is similar to the jump-to-subroutine (JSR) instruction.

When CALL is executed, the current value in PPAGE is pushed onto the

stack with a return address, and a new instruction-supplied value is written

to PPAGE. This value selects the page the called subroutine resides upon

and can be considered part of the effective address. For all addressing

mode variations except indexed indirect modes, the new page value is

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