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HCS12 데이터시트(PDF) 98 Page - Freescale Semiconductor, Inc

부품명 HCS12
상세설명  HCS12 Microcontrollers
PDF  452 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

HCS12 데이터시트(HTML) 98 Page - Freescale Semiconductor, Inc

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S12CPUV2 Reference Manual, Rev. 4.0
98
Freescale Semiconductor
U — Unstack 16-bit data. These cycles are extended to two
bus cycles if the MCU is operating with an 8-bit
external data bus and the SP is pointing to external
memory. There can be additional stretching when the
address space is assigned to a chip-select circuit
programmed for slow memory. These cycles are also
stretched if they correspond to misaligned accesses
to a memory that is not designed for single-cycle
misaligned access. The internal RAM is designed to
allow single-cycle misaligned word access.
V — Vector fetch. Vectors are always aligned 16-bit words.
These cycles are extended to two bus cycles if the
MCU is operating with an 8-bit external data bus and
the program is stored in external memory. There can
be additional stretching when the address space is
assigned to a chip-select circuit programmed for slow
memory.
t — 8-bit conditional read. These cycles are either data
read cycles or unused cycles, depending on the data
and flow of the REVW instruction. These cycles are
stretched only when controlled by a chip-select circuit
programmed for slow memory.
T — 16-bit conditional read. These cycles are either data
read cycles or free cycles, depending on the data and
flow of the REV or REVW instruction. These cycles
are extended to two bus cycles if the MCU is operating
with an 8-bit external data bus and the corresponding
data is stored in external memory. There can be
additional stretching when the address space is
assigned to a chip-select circuit programmed for slow
memory. These cycles are also stretched if they
correspond to misaligned accesses to a memory that
is not designed for single-cycle misaligned access.
x — 8-bit conditional write. These cycles are either data
write cycles or free cycles, depending on the data and
flow of the REV or REVW instruction. These cycles
are only stretched when controlled by a chip-select
circuit programmed for slow memory.



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