전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

HCS12 데이터시트(PDF) 327 Page - Freescale Semiconductor, Inc

부품명 HCS12
상세설명  HCS12 Microcontrollers
PDF  452 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

HCS12 데이터시트(HTML) 327 Page - Freescale Semiconductor, Inc

Back Button HCS12 Datasheet HTML 323Page - Freescale Semiconductor, Inc HCS12 Datasheet HTML 324Page - Freescale Semiconductor, Inc HCS12 Datasheet HTML 325Page - Freescale Semiconductor, Inc HCS12 Datasheet HTML 326Page - Freescale Semiconductor, Inc HCS12 Datasheet HTML 327Page - Freescale Semiconductor, Inc HCS12 Datasheet HTML 328Page - Freescale Semiconductor, Inc HCS12 Datasheet HTML 329Page - Freescale Semiconductor, Inc HCS12 Datasheet HTML 330Page - Freescale Semiconductor, Inc HCS12 Datasheet HTML 331Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 327 / 452 page
background image
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
327
8.3.3 Null (Code 0:0)
The 0:0 data movement state indicates that there was no data movement in
the instruction queue; the 0:0 execution start state indicates continuation of
an instruction or interrupt sequence (no new instruction or interrupt start).
8.3.4 LAT — Latch Data from Bus (Code 0:1)
This code is not used in the HCS12. In the M68HC12, fetched program
information has arrived, but the queue is not ready to advance. The
information is latched into a buffer. Later, when the queue does advance,
stage 1 is refilled from the buffer or from the data bus if the buffer is empty.
In some instruction sequences, there can be several latch cycles before the
queue advances. In these cases, the buffer is filled on the first latch event
and additional latch requests are ignored.
8.3.5 ALD — Advance and Load from Data Bus (Code 1:0)
The instruction queue is advanced by one word and stage one is refilled with
a word of program information from the data bus. The CPU requested the
information two bus cycles earlier but, due to access delays, the information
was not available until the E cycle referred to by the ALD code.
8.3.6 ALL — Advance and Load from Latch (Code 1:1)
This code is not used in the HCS12. In the M68HC12, the 2-stage instruction
queue is advanced by one word and stage one is refilled with a word of
program information from the buffer. The information was latched from the
data bus at the falling edge of a previous E cycle because the instruction
queue was not ready to advance when it arrived.
8.3.7 INT — Interrupt Sequence Start (Code 0:1)
The E cycle associated with this code is the first cycle of an interrupt
sequence. Normally, this cycle is a read of the interrupt vector. However, in
systems that have interrupt vectors in external memory and an 8-bit data
bus, this cycle reads the upper byte of the 16-bit interrupt vector.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com