HCS12 datasheet(359/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

359

9.5.2 Weighted Rule Evaluation (REVW)

This instruction implements a weighted variation of min-max rule evaluation.

The weighting factors are stored in a table with one 8-bit entry per rule. The

weight is used to multiply the truth value of the rule (minimum of all

antecedents) by a value from zero to one to get the weighted result. This

weighted result is then applied to the consequents, just as it would be for

unweighted rule evaluation.

Since the REVW instruction is essentially a list-processing instruction,

execution time is dependent on the number of rules and the number of

elements in the rule list. The REVW instruction is interruptible (typically

within three to five bus cycles), so it does not adversely affect worst case

interrupt latency. Since all intermediate results and instruction status are

held in stacked CPU registers, the interrupt service code can even include

independent REV and REVW instructions.

The rule structure is different for REVW than for REV. For REVW, the rule

list is made up of 16-bit elements rather than 8-bit elements. Each

antecedent is represented by the full 16-bit address of the corresponding

fuzzy input. Each rule consequent is represented by the full address of the

corresponding fuzzy output.

The markers separating antecedents from consequents are the reserved

16-bit value $FFFE, and the end of the last rule is marked by the reserved

16-bit value $FFFF. Since $FFFE and $FFFF correspond to the addresses

of the reset vector, there would never be a fuzzy input or output at either of

these locations.

9.5.2.1 Set Up Prior to Executing REVW

Some CPU registers and memory locations need to be set up prior to

executing the REVW instruction. X and Y index registers are used as index

pointers to the rule list and the list of rule weights. The A accumulator is used

for intermediate calculation results and needs to be set to $FF initially. The

V condition code bit is used as an instruction status indicator that shows

whether antecedents or consequents are being processed. Initially the V bit

is cleared to zero to indicate antecedents are being processed. The C

condition code bit is used to indicate whether rule weights are to be used (1)

or not (0). The fuzzy outputs (working RAM locations) need to be cleared to

$00. If these values are not initialized before executing the REVW

instruction, results will be erroneous.

The X index register is set to the address of the first element in the rule list

(in the knowledge base). The REVW instruction automatically updates this

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