HCS12 datasheet(368/452 Pages) FREESCALE

368 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

368

Freescale Semiconductor

In cycle 2.0, three internal 16-bit temporary registers are cleared in

preparation for summation operations, but there is no bus access. The WAV

instruction maintains a 32-bit sum-of-products in TMP1 : TMP2 and a 16-bit

sum-of-weights in TMP3. By keeping these sums inside the CPU, bus

accesses are reduced and the WAV operation is optimized for high speed.

Cycles 3.0 through 9.0 form the 7-cycle main loop for WAV. The value in the

8-bit B accumulator is used to count the number of loop iterations. B is

decremented at the top of the loop in cycle 3.0, and the test for zero is

located at the bottom of the loop after cycle 9.0. Cycle 4.0 and 5.0 are used

to fetch the 8-bit operands for one iteration of the loop. X and Y index

registers are used to access these operands. The index registers are

incremented as the operands are fetched. Cycle 6.0 is used to accumulate

the current fuzzy output into TMP3. Cycles 7.0 through 9.0 are used to

perform the eight by eight multiply of Fi times Si, and accumulate this result

into TMP1 : TMP2. Even though the sum-of-products will not exceed 24 bits,

the sum is maintained in the 32-bit combined TMP1 : TMP2 register

because it is easier to use existing 16-bit operations than it would be to

create a new smaller operation to handle the high order bits of this sum.

Since the weighted average operation could be quite long, it is made to be

interruptible. The usual longest latency path is from very early in cycle 6.0,

through cycle 9.0, to the top of the loop to cycle 3.0, through cycle 5.0 to the

interrupt check.

If the WAV instruction is interrupted, the internal temporary registers TMP3,

TMP2, and TMP1 need to be stored on the stack so the operation can be

resumed. Since the WAV instruction included initialization in cycle 2.0, the

recovery path after an interrupt needs to be different. The wavr

pseudo-instruction has the same opcode as WAV, but it is on the first page

of the opcode map so there is no page prebyte ($18) like there is for WAV.

When WAV is interrupted, the PC is adjusted to point at the second byte of

the WAV object code, so that it will be interpreted as the wavr

pseudo-instruction on return from the interrupt, rather than the WAV

instruction. During the recovery sequence, the PC is readjusted in case

another interrupt comes before the weighted average operation finishes.

The resume sequence includes recovery of the temporary registers from the

stack (1.1 through 3.1), and reads to get the operands for the current

iteration. The normal WAV flow is then rejoined at cycle 6.0.

Upon normal completion of the instruction (cycle 10.0), the PC is adjusted

so it points to the next instruction. The results are transferred from the TMP

registers into CPU registers in such a way that the EDIV instruction can be

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