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HCS12 데이터시트(PDF) 422 Page - Freescale Semiconductor, Inc

부품명 HCS12
상세설명  HCS12 Microcontrollers
PDF  452 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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HCS12 데이터시트(HTML) 422 Page - Freescale Semiconductor, Inc

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S12CPUV2 Reference Manual, Rev. 4.0
422
Freescale Semiconductor
These instructions can also be used to limit a data value prior to using it as
an input to a table lookup or other routine. Suppose a table is valid for input
values between $20 and $7F. An arbitrary input value can be tested against
these limits and be replaced by the largest legal value if it is too big, or the
smallest legal value if too small using the following two CPU12 instructions.
HILIMIT
FCB
$7F
;comparison value needs to be in mem
LOWLIMIT
FCB
$20
;so it can be referenced via indexed
MINA
HILIMIT,PCR
;A=MIN(A,$7F)
MAXA
LOWLIMIT,PCR
;A=MAX(A,$20)
;A now within the legal range $20 to $7F
The “,PCR” notation is also new for the CPU12. This notation indicates the
programmer wants an appropriate offset from the PC reference to the
memory location (HILIMIT or LOWLIMIT in this example), and then to
assemble this instruction into a PC-relative indexed MIN or MAX instruction.
B.8.6 Fuzzy Logic Support
The CPU12 includes four instructions (MEM, REV, REVW, and WAV)
specifically designed to support fuzzy logic programs. These instructions
have a very small impact on the size of the CPU and even less impact on
the cost of a complete MCU. At the same time, these instructions
dramatically reduce the object code size and execution time for a fuzzy logic
inference program. A kernel written for the M68HC11 required about 250
bytes and executed in about 750 milliseconds. The CPU12 kernel uses
about 50 bytes and executes in about 16 microseconds (in a 25-MHz
HCS12).
B.8.7 Table Lookup and Interpolation
The CPU12 instruction set includes two instructions (TBL and ETBL) for
lookup and interpolation of compressed tables. Consecutive table values
are assumed to be the x coordinates of the endpoints of a line segment. The
TBL instruction uses 8-bit table entries (y-values) and returns an 8-bit result.
The ETBL instruction uses 16-bit table entries (y-values) and returns a
16-bit result.
An indexed addressing mode is used to identify the effective address of the
data point at the beginning of the line segment, and the data value for the
end point of the line segment is the next consecutive memory location (byte
for TBL and word for ETBL). In both cases, the B accumulator represents
the ratio of (the x-distance from the beginning of the line segment to the
lookup point) to (the x-distance from the beginning of the line segment to the
end of the line segment). B is treated as an 8-bit binary fraction with radix



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