LTC690/LTC691

LTC694/LTC695

11

690fe

APPLICATIONS INFORMATION

If battery connections are made through long wires, a

10Ω to 100Ω series resistor and a 0.1μF capacitor are

to the lead inductance (Figure 4).

4.3M

0.1μF

LTC690

LTC691

LTC694

LTC695

GND

690 F04

10Ω

Figure 4. 10Ω/0.1μF Combination Eliminates Inductive

Overshoot and Prevents Spurious Resets During Battery

Replacement

Table 1 shows the state of each pin during battery back-up.

When the battery switchover section is not used, connect

Memory Protection

The LTC691 and LTC695 include memory protection

circuitry that ensures the integrity of the data in memory

Two additional pins, CE IN and CE OUT, control the Chip

CE OUT follows CE IN with a typical propagation delay of

OUT is an alternative signal to drive the CE, CS, or Write

input of battery-backed up CMOS RAM. CE OUT can also

be used to drive the Store or Write input of an EEPROM,

EAROM or NOVRAM to achieve similar protection. Figure

5 shows the timing diagram of CE IN and CE OUT.

CE IN can be derived from the microprocessor’s address

decoder output. Figure 6 shows a typical nonvolatile CMOS

RAM application.

Memory protection can also be achieved with the LTC690

and LTC694 by using RESET as shown in Figure 7.

Table 1. Input and Output Status in Battery Back-Up Mode

SIGNAL

STATUS

The supply current is 1μA maximum.

BATT ON

PFI

Power failure input is ignored.

PFO

Logic low

RESET

Logic low

RESET

LOW⎯LINE Logic low

WDI

Watchdog input is ignored.

WDO

CE IN

Chip⎯Enable Input is ignored.

CE OUT

OSC IN

OSC IN is ignored.

OSC SEL

OSC SEL is ignored.

V1

CE IN

CE OUT

V2

V1 = RESET VOLTAGE THRESHOLD

V2 = RESET VOLTAGE THRESHOLD +

RESET THRESHOLD HYSTERESIS

690 F05

Figure 5. Timing Diagram for CE IN and CE OUT