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LTC695CSWPBF 데이터시트(PDF) 14 Page - Linear Technology

부품명 LTC695CSWPBF
상세설명  Microprocessor Supervisory Circuits
PDF  18 Pages
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LTC695CSWPBF 데이터시트(HTML) 14 Page - Linear Technology

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LTC690/LTC691
LTC694/LTC695
14
690fe
The LTC691 and LTC695 provide an additional output
(Watchdog Output, WDO) which goes low if the watchdog
timer is allowed to time out and remains low until set high
by the next transition on the WDI pin. WDO is also set high
when VCC falls below the reset voltage threshold or VBATT.
The LTC691 and LTC695 have two additonal pins OSC SEL
and OSC IN, which allow reset active time and watchdog
timeout period to be adjusted per Table 2. Several
configurations are shown in Figure 12.
OSC IN can be driven by an external clock signal or an
external capacitor can be connected between OSC IN and
APPLICATIONS INFORMATION
GND when OSC SEL is forced low. In these configurations,
the nominal reset active time and watchdog timeout
period are determined by the number of clocks or set by
the formula in Table 2. When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 35ms minimum for the LTC691 and 140ms
minimum for the LTC695. OSC IN selectes between the
1 second and 70ms minimum normal watchdog timeout
periods. In both cases, the timeout period immediately
after a reset is at least 1 second.
t1 = RESET ACTIVE TIME
t2 = NORMAL WATCHDOG TIME-OUT PERIOD
t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY
AFTER A RESET
VCC = 5V
t2
t3
t1
t1
WDO
WDI
RESET
690 F11
EXTERNAL CLOCK
INTERNAL OSCILLATOR
1.6 SECOND WATCHDOG
INTERNAL OSCILLATOR
100ms WATCHDOG
EXTERNAL OSCILLATOR
GND
GND
GND
GND
VCC
VCC
VCC
OSC SEL
OSC SEL
OSC SEL
OSC SEL
OSC IN
OSC IN
OSC IN
OSC IN
3
3
3
3
4
4
4
4
8
8
8
8
7
7
7
7
VCC
FLOATING
OR HIGH
FLOATING
OR HIGH
LTC691
LTC695
FLOATING
OR HIGH
LTC691
LTC695
LTC691
LTC695
LTC691
LTC695
690 F12
5V
5V
5V
5V
Figure 11. Watchdog Timeout Period and Reset Active Time
Figure 12. Oscillator Configurations



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