68HC05CL48 datasheet(55/145 Pages) MOTOROLA

55 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

TIMER

MOTOROLA

REV 2.0

8-3

8.1.1 Counter

The key element in the programmable timer is a 16-bit, free-running counter or

counter register, preceded by a prescaler that divides the internal processor clock

by four. The prescaler gives the timer a resolution of 2.2 microseconds if the

internal bus clock is 1.8MHz. The counter is incremented during the low portion of

the internal bus clock. Software can read the counter at any time without affecting

its value.

The double-byte, free-running counter can be read from either of two locations,

$19-$1A (counter register) or $1B-$1C (counter alternate register). A read from

only the least signiﬁcant byte (LSB) of the free-running counter ($1A, $1C)

receives the count value at the time of the read. If a read of the free-running

76543210

TCH

$0019

READ

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

WRITE

RESET

11111111

76543210

TCL

$001A

READ

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

WRITE

Counter Reset

RESET

11111100

76543210

ACH

$001B

READ

AC15

AC14

AC13

AC12

AT11

AC10

AC9

AC8

WRITE

RESET

11111111

76543210

ACL

$001C

READ

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

WRITE

Counter Reset

RESET

11111100

68HC05CL48 데이터시트(PDF) 55 Page - Motorola, Inc

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