68HC05CL48 datasheet(67/145 Pages) MOTOROLA

67 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

TIMER

MOTOROLA

REV 2.0

8-15

timer chain. This circuit is followed by two more stages, with the resulting clock (E/

16384) driving the Real Time Interrupt circuit. The RTI circuit consists of three

divider stages with a 1 of 4 selector. The output of the RTI circuit is further divided

by eight to drive the optional COP Watchdog Timer circuit. The RTI rate selector

bits, and the RTI and CTOF enable bits and ﬂags are located in the Ctimer Control

and Status Register(CTCSR) at location $08.

Figure 8-6. Core Timer Block Diagram

COP

Clear

Internal Bus

$09 CTCR

7-bit counter

Interrupt Circuit

$08 CTCSR

RTI Select Circuit

Overﬂow

Circuit

Detect

COP Watchdog

Resetable Timer(

÷8)

To Interrupt

Logic

fop

fop/2

POR

TCBP

TCSR

TCR

Internal

Processor

Clock

RTIF

CTimer Control & Status Register

Core Timer Counter Register (TCR)

÷4

CTOFE

RTIE

CTOF

RT1

RT0

To Reset

Logic

68HC05CL48 데이터시트(PDF) 67 Page - Motorola, Inc

68HC05CL48 데이터시트(HTML) 67 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL