68HC05CL48 datasheet(74/145 Pages) MOTOROLA

74 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

SERIAL PERIPHERAL INTERFACE

MC68HC05CL48

9-2

REV 2.0

9.1.2 MOSI Serial Data In (Input)

9.1.2.1

Slave Mode

MOSI is the signal used to receive data from some Master device. Figure 9-1

shows the serial clock and data timing relationship.

It should be noted that when a Master device transmits data to a second device

via the MOSI line, the slave device (if it has the capability) will respond by sending

data into the MISO pin of the master device. This implies full duplex transmission

with both data-out and data-in synchronized to the same clock signal which is

provided by the master. Moreover, the SAME shift register is used for data out and

data in. Thus, the byte transmitted is replaced by the byte received, removing the

need for separate status bits for XMIT EMPTY and REC FULL. A single status bit,

SPIF, is used to signify IO operation complete.

9.1.2.2

Master Mode

As noted above, the function of MOSI and MISO are inverted in the master mode.

The MOSI pin becomes the data output pin when the device is in the master

mode. When a transfer of data is not taking place with a Slave device the Master

drives the MOSI line high. The Master always allows the data onto the MOSI pin a

half-cycle before the clock edge (SCK) needed for the Slave to latch the data

internally.

9.1.3 SCK Serial Clock (In/Out)

9.1.3.1

Slave Mode

The serial clock is used to move data both in and out of the device through its

MOSI and MISO pins. The Master and Slave device are capable of exchanging a

byte of information during a sequence of eight clock pulses if wired to do so. In the

slave mode, the SCK pin becomes an input for the external clock being sent from

the Master device. In this case SCK is asynchronous to the Slave device’s phase

1-2 clocks and read/write control, therefore synchronization must take place prior

to transmission and after reception. This must be done on the byte level. The type

of clock and its’ relationship with the data is controlled by bits CPOL and CPHA.

Reference Figure 9-1. The clock rate control bits SPR1 and SPR0 have no

function while the part is in the Slave mode.

9.1.3.2

Master Mode

In this mode, the clock is generated within the Master device by a circuit driven

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