PC912XDP512F0MFVR datasheet(32/1348 Pages) FREESCALE

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Chapter 1 Device Overview MC9S12XD-Family

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1.1.1

MC9S12XD/B/A Family Features

This section lists the features which are available on

MC9S12XDP512RMV2. See Appendix E Derivative Differences for

availability of features and memory sizes on other family members.

•

HCS12X Core

— 16-bit HCS12X CPU

– Upward compatible with MC9S12 instruction set

– Interrupt stacking and programmer’s model identical to MC9S12

– Instruction queue

– Enhanced indexed addressing

– Enhanced instruction set

— EBI (external bus interface)

— MMC (module mapping control)

— INT (interrupt controller)

— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)

— BDM (background debug mode)

•

XGATE (peripheral coprocessor)

— Parallel processing module off loads the CPU by providing high-speed data processing and

transfer

— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports

•

PIT (periodic interrupt timer)

— Four timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

•

CRG (clock and reset generator)

— Low noise/low power Pierce oscillator

— PLL

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake-up from stop mode

•

Port H & Port J with interrupt functionality

— Digital ﬁltering

— Programmable rising or falling edge trigger

•

Memory

— 512, 256 and 128-Kbyte Flash EEPROM

— 4 and 2-Kbyte EEPROM

— 32, 16 and 12-Kbyte RAM

•

One 16-channel and one 8-channel ADC (analog-to-digital converter)

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