PC912XDP512F0MFVR datasheet(52/1348 Pages) FREESCALE

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Chapter 1 Device Overview MC9S12XD-Family

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1.2.2

Signal Properties Summary

Table 1-7 summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts

of the S12XD, S12XB and S12XA family please refer to Appendix E Derivative Differences.

Table 1-7. Signal Properties Summary (Sheet 1 of 4)

Name

Function 1

Name

Function 2

Name

Function 3

Name

Function 4

Name

Function 5

Power

Supply

Internal Pull

Resistor

Description

CTRL

Reset

State

EXTAL

—

VDDPLL

Oscillator pins

XTAL

—

VDDPLL

RESET

—

VDDR

PULLUP

External reset

TEST

—

N.A.

RESET pin

DOWN Test input

VREGEN

—

VDDX

PUCR

Voltage regulator enable

Input

XFC

—

VDDPLL

PLL loop ﬁlter

BKGD

MODC

—

VDDX

Always on

Background debug

PAD[23:08]

AN[23:8]

—

VDDA

PER0/

PER1

Disabled Port AD I/O, Port AD inputs

of ATD1 and

analog inputs of ATD1

PAD[07:00]

AN[7:0]

—

VDDA

PER1

Disabled Port AD I/O, Port AD inputs

of ATD0 and

analog inputs of ATD0

PA[7:0]

—

VDDR

PUCR

Disabled Port A I/O

PB[7:0]

—

VDDR

PUCR

Disabled Port BI/O

PA[7:0]

ADDR[15:8]

IVD[15:8]

—

VDDR

PUCR

Disabled Port A I/O, address bus,

internal visibility data

PB[7:1]

ADDR[7:1]

IVD[7:0]

—

VDDR

PUCR

Disabled Port B I/O, address bus,

internal visibility data

PB0

ADDR0

UDS

VDDR

PUCR

Disabled Port B I/O, address bus,

upper data strobe

PC[7:0]

DATA[15:8]

—

VDDR

PUCR

Disabled Port C I/O, data bus

PD[7:0]

DATA[7:0]

—

VDDR

PUCR

Disabled Port D I/O, data bus

PE7

ECLKX2

XCLKS

—

VDDR

PUCR

Port E I/O, system clock

output, clock select

PE6

TAGHI

MODB

—

VDDR

While RESET

pin is low: down

Port E I/O, tag high, mode

input

PE5

MODA

TAGLO

—

VDDR

While RESET

pin is low: down

Port E I/O, read enable,

mode input, tag low input

PE4

ECLK

—

VDDR

PUCR

Port E I/O, bus clock output

PE3

LSTRB

LDS

EROMCTL

—

VDDR

PUCR

Port E I/O, low byte data

strobe, EROMON control

PE2

R/W

—

VDDR

PUCR

Port E I/O, read/write

PE1

IRQ

—

VDDR

PUCR

Port E Input, maskable

interrupt

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