PC912XDP512F0MFVR datasheet(71/1348 Pages) FREESCALE

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Chapter 1 Device Overview MC9S12XD-Family

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1.5

Modes of Operation

1.5.1

User Modes

1.5.1.1

Normal Expanded Mode

Ports K, A, and B are conﬁgured as a 23-bit address bus, ports C and D are conﬁgured as a 16-bit data bus,

and port E provides bus control and status signals. This mode allows 16-bit external memory and

peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the

internal bus rate.

1.5.1.2

Normal Single-Chip Mode

There is no external bus in this mode. The processor program is executed from internal memory. Ports A,

B,C,D, K, and most pins of port E are available as general-purpose I/O.

1.5.1.3

Special Single-Chip Mode

This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The

background debug module BDM is active in this mode. The CPU executes a monitor program located in

an on-chip ROM. BDM ﬁrmware is waiting for additional serial commands through the BKGD pin. There

is no external bus after reset in this mode.

1.5.1.4

Emulation of Expanded Mode

Developers use this mode for emulation systems in which the users target application is normal expanded

mode. Code is executed from external memory or from internal memory depending on the state of

ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.

1.5.1.5

Emulation of Single-Chip Mode

Developers use this mode for emulation systems in which the user’s target application is normal

single-chip mode. Code is executed from external memory or from internal memory depending on the state

of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.

1.5.1.6

Special Test Mode

Freescale internal use only.

1.5.2

Low-Power Modes

The microcontroller features two main low-power modes. Consult the respective sections for information

on the module behavior in system stop, system pseudo stop, and system wait mode. An important source

of information about the clock system is the Clock and Reset Generator S12CRG section.

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