PC912XDP512F0MFVR datasheet(56/1348 Pages) FREESCALE

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Chapter 1 Device Overview MC9S12XD-Family

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1.2.3.3

TEST — Test Pin

This input only pin is reserved for test. This pin has a pulldown device.

NOTE

The TEST pin must be tied to VSS in all applications.

1.2.3.4

VREGEN — Voltage Regulator Enable Pin

This input only pin enables or disables the on-chip voltage regulator. The input has a pullup device.

1.2.3.5

XFC — PLL Loop Filter Pin

Please ask your Freescale representative for the interactive application note to compute PLL loop ﬁlter

elements. Any current leakage on this pin must be avoided.

Figure 1-10. PLL Loop Filter Connections

1.2.3.6

BKGD / MODC — Background Debug and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It

is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit

at the rising edge of RESET. The BKGD pin has a pullup device.

1.2.3.7

PAD[23:8] / AN[23:8] — Port AD Input Pins of ATD1

PAD[23:8] are general-purpose input or output pins and analog inputs AN[23:8] of the analog-to-digital

converter ATD1.

1.2.3.8

PAD[7:0] / AN[7:0] — Port AD Input Pins of ATD0

PAD[7:0] are general-purpose input or output pins and analog inputs AN[7:0] of the analog-to-digital

converter ATD0.

1.2.3.9

PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD1

PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital

converter ATD1.

MCU

XFC

VDDPLL

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