KM416RD8AS-RBM80 datasheet(31/64 Pages) SAMSUNG

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Page 28

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

Initialization

Initialization refers to the process that a controller must go

through after power is applied to the system or the system is

reset. The controller prepares the RDRAM sub-system for

normal Channel operation by using a sequence of control

The first step in this sequence is to assign unique serial

device addresses to all the RDRAMs. This is done with

Algorithm InitDev, shown in the opposite column. The

controller assumes that there are no more that “N” RDRAMs

on the Channel (the Channel maximum is 32, but some

applications may have a lower limit).

First, the SIO0 and SIO1 pin directionality is established

with the sequence in step 1. The controller then resets all

RDRAMs, using broadcast SETR and CLRR commands

(steps 2,3,4,5) with a delay in between (this is also called

SIO Reset). In step 6, a SETF command establishs the

normal clock frequency. See Figure 25 for the format of

SETR, CLRR, and SETF transactions. In step 7 the SIO0-to-

SIO1 link is broken in all RDRAMs, so the controller is only

talking to the first RDRAM. Also, the SDEVID field is set to

its maximum value. Next, the loop index INDX is initialized

(step 8). In step 9, the SDEVID field is loaded with the

INDX value, and the SRP bit is set so the next RDRAM

becomes accessible. In step 10, the INDX value is incre-

mented, and in step 11, steps 8 and 9 are repeated for the

remaining RDRAMs.

Finally, it will be necessary for the controller to force a

200

µs pause interval to allow the RDRAM core timing

circuits to stabilize. All banks of all RDRAMs must also be

accessed twice. An access is an activate (ACT) and a

precharge (PRE) command. This may be accomplished with

the refresh commands.

At this point, Algorithm InitDev is complete and all

RDRAMs have a unique device address SDEVID5..0 for

control register transactions. Note that the SDEVID address

value of an RDRAM indicates its position in the daisy-

chained CMOS serial pins. This will not necessarily be the

same value as the DEVID register which is used for memory

transactions. The next steps taken by the controller will vary

depending upon the application, so only a rough outline can

be given here.

=======================================

Algorithm InitDev: Assign SDEVID Device Addresses

Issue SIO Reset sequence (see Figure 26).

Issue one SETR transaction:

• SOP3..SOP0 = 0010 (SETR command)

• SBC = 1 (Broadcast)

• SDEV5..SDEV0 = 000000 (don’t care).

Wait 16 SCK cycles.

Issue one CLRR transaction:

• SOP3..SOP0 = 0011 (CLRR command)

• SBC = 1 (Broadcast)

• SDEV5..SDEV0 = 000000 (don’t care).

Wait 4 SCK cycles.

Issue one SETF transaction:

• SOP3..SOP0 = 0100 (SETF command)

• SBC = 1 (Broadcast)

• SDEV5..SDEV0 = 000000 (don’t care).

Wait 4 SCK cycles.

Issue one register write transaction:

• SOP3..SOP0 = 0001 (SWR command)

• SBC = 1 (broadcast)

• SDEV5..SDEV0 = 000000 (don’t care).

• SA11..SA0 = 021 16 (INIT control register).

• SD15..SD0 = 401f 16 (SRP<=0, SDEVID<=3f).

Set INDX5..INDX0 to 00000002. INDX is a counter in the

Controller which acts as a loop index.

10.

Issue one register write transaction (SRP<=1, SDEVID<=INDX):

• SOP3..SOP0 = 0001 (SWR command)

• SBC = 0 (non-broadcast)

•SDEV5..SDEV0 = 111111.

• SA11..SA0 = 021 16 (INIT control register).

• SD15..SD0 = {0 2, INDX5, 000001002, INDX4..INDX0}.

11.

Increment INDX5..INDX0.

12.

Repeat Steps (8) and (9) an additional (N-1) times.

13.

tPAUSE delay, then tPDNXA+ tPDNXB delay (to allow DLLs to lock),

then access all banks twice from a precharged state; i.e perform one of

the two following two (broadcast) sequences to each bank of all

RDRAMs:

a. REFA/REFP, REFA/REFP, REFA/REFP or

a. REFP, REFA/REFP, REFA/REFP

Figure 26: SIO Reset Sequence

SCK

CMD

SIO0

T16

0000000000000000

00000000...00000000

0000000000000000

1100

SIO1

The packet is repeated

from SIO0 to SIO1

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