| 전자부품 데이터시트 검색엔진 |
|
910GL 데이터시트(PDF) 77 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
910GL 데이터시트(HTML) 77 Page - Intel Corporation |
|
77 / 426 page ![]() Host Bridge/DRAM Controller Registers (D0:F0) R Datasheet 77 4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) PCI Device: 0 Address Offset: 4Ch Default Value: 00000000h Access: R/W Size: 32 bits This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express hierarchy associated with the (G)MCH. There is no physical memory within this 4-KB window that can be addressed. The 4 KB that is reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, this register is disabled and must be enabled by writing a 1 to the DMIBAREN [Dev 0, offset 54h, bit 29]. | Bit Access & Default Description 31:12 R/W 0000 0h DMI Base Address: This field corresponds to bits 31 to 12 of the base address DMI configuration space. BIOS will program this register resulting in a base address for a 4-KB block of contiguous memory address space. This register ensures that a naturally aligned 4-KB space is allocated within total addressable memory space of 4 GB. System software uses this base address to program the DMI register set. 11:0 Reserved |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |