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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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910GL 데이터시트(PDF) 98 Page - Intel Corporation |
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910GL 데이터시트(HTML) 98 Page - Intel Corporation |
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98 / 426 page  MCHBAR Registers R 98 Datasheet 5.1.2 C0DRB1—Channel A DRAM Rank Boundary Address 1 MMIO Range: MCHBAR Address Offset: 101h Default Value: 00h Access: R/W Size: 8 bits The operation of this register is detailed in the description for register C0DRB0. 5.1.3 C0DRB2—Channel A DRAM Rank Boundary Address 2 MMIO Range: MCHBAR Address Offset: 102h Default Value: 00h Access: R/W Size: 8 bits The operation of this register is detailed in the description for register C0DRB0. 5.1.4 C0DRB3—Channel A DRAM Rank Boundary Address 3 MMIO Range: MCHBAR Address Offset: 103h Default Value: 00h Access: R/W Size: 8 bits The operation of this register is detailed in the description for register C0DRB0. |
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